8-Bit Processor To S1D13706 Interface; Hardware Connections - Epson S1D13706 Technical Manual

Embedded memory lcd controller

Hide thumbs Also See for S1D13706:

Table of Contents

Epson Research and Development

Vancouver Design Center

4 8-Bit Processor to S1D13706 Interface

Generic 8-bit Bus

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of 8-bit Processor to S1D13706 Interface

Interfacing to 8-bit Processors

Issue Date: 01/02/23

The interface between the S1D13706 and an 8-bit processor requires minimal glue logic. A

decoder is used to generate the chip select for the S1D13706 based on where the S1D13706

is mapped into memory. Alternatively, if the processor supports a chip select module, it can

be programmed to generate a chip select for the S1D13706 without the need of an address

An inverter inverts A0 to generate the BHE# signal for the S1D13706. If the 8-bit host

interface has an active high WAIT signal, it must be inverted as well.

BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and should

be tied high (connected to HIO V

In order to support an 8-bit processor with a 16-bit peripheral, the low and high order bytes

of the data bus must be connected together. The following diagram shows a typical imple-

mentation of an 8-bit processor to S1D13706 interface.

System RESET

X31B-G-015-02

Table of Contents