Table 8-17: Pwm Clock Divide Select Options; Table 8-18: Cv Pulse Divide Select Options - Epson S1D13706 Technical Manual

Page 128
PWM Clock / CV Pulse Configuration Register
REG[B1h]
PWM Clock Divide Select Bits 3-0
7 6
bits 7-4
PWM Clock Divide Select Bits [3:0]
bits 3-1
CV Pulse Divide Select Bits [2:0]
bit 0
S1D13706
X31B-A-001-08
5
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.

Table 8-17: PWM Clock Divide Select Options

0h
1h
2h
3h
...
Ch
Dh-Fh
Note
This divided clock is further divided by 256 before it is output at PWMOUT.
CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse source is
divided.

Table 8-18: CV Pulse Divide Select Options

0h
1h
2h
3h
...
7h
Note
This divided clock is further divided by 2 before it is output at the CVOUT.
PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is CLKI2.
Note
For further information on the PWMCLK source select, see Section 7.2, "Clock Selec-
tion" on page 93.
CV Pulse Divide Select Bits 2-0
4 3
PWM Clock Divide Amount
CV Pulse Divide Amount
Epson Research and Development
Vancouver Design Center
2 1
1
2
4
8
...
4096
Reserved
1
2
4
8
...
128
Hardware Functional Specification
Issue Date: 01/11/13
Read/Write
PWMCLK
Source Select
0