Epson S1D13706 Technical Manual page 272

Page 12
S1D13706
X31B-B-001-03
BCLK
Source
Divide
Timing
MCLK
Source
Divide
Timing
These settings select the clock signal source and divisor
for the bus interface clock (BCLK).
The BCLK source is CLKI.
Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the BCLK source to derive
BCLK.
This field shows the actual BCLK frequency used by
the configuration process.
These settings select the clock signal source and input
clock divisor for the memory clock (MCLK). MCLK
should be set as close to the maximum (50 MHz) as
possible.
The MCLK source is BCLK.
Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the MCLK source to
derive MCLK.
This divide ratio should be left at 1:1 unless the
resultant MCLK is greater that 50MHz.
This field shows the actual MCLK frequency used by
the configuration process.
Epson Research and Development
Vancouver Design Center
13706CFG Configuration Program
Issue Date: 01/03/29