Table 6-10: Motorola Mc68K #2 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Bus Clock frequency
CLK
T Bus Clock period
CLK
t1 Clock pulse width high
t2 Clock pulse width low
A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where
t3
CS# = 0, AS# = 0, DS# = 0
t4 A[16:0], SIZ[1:0], M/R# hold from AS# rising edge
t5 CS# setup to CLK rising edge
t6 CS# hold from AS# rising edge
t7a AS# asserted for MCLK = BCLK
AS# asserted for MCLK = BCLK ÷ 2
t7b
AS# asserted for MCLK = BCLK ÷ 3
t7c
AS# asserted for MCLK = BCLK ÷ 4
t7d
t8 AS# falling edge to CLK rising edge
t9 AS# rising edge to CLK rising edge
t10 DS# falling edge to CLK rising edge
t11 DS# setup to CLK rising edge
t12 First CLK where AS# = 1 to DSACK1# high impedance
R/W# setup to CLK rising edge before all CS# = 0, AS# = 0, and
t13
DS# = 0
t14 R/W# hold from AS# rising edge
t15 AS# = 0 and CS# = 0 to DSACK1# rising edge
t16 AS# rising edge to DSACK1# rising edge
D[31:16] valid to third CLK rising edge where CS# = 0, AS# = 0,
t17
and DS# = 0 (write cycle) (see note 1)
t18 D[31:16] hold from falling edge of DSACK1# (write cycle)
t19 DS# falling edge to D[31:16] driven (read cycle)
t20 DSACK1# falling edge to D[31:16] valid (read cycle)
t21 DS# rising edge to D[31:16] invalid/high impedance (read cycle)
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-10: Motorola MC68K #2 Interface Timing

Parameter
2.0V 3.3V
Min Max Min
20
1/f 1/f
CLK CLK
22.5 9
22.5 9
1 1
0 0
0 1
0 0
8
11
13
18
1 1
1 3
1 1
1 3
5 40 3
1 1
0 0
4 23 3
6 39 4
1 0
0 0
4 32 3
0
5 36 3
Page 47
Unit
Max
50 MHz
ns
ns
ns
ns
ns
ns
ns
8 T
CLK
11 T
CLK
13 T
CLK
18 T
CLK
ns
ns
ns
ns
14 ns
ns
ns
14 ns
17 ns
ns
ns
14 ns
2 ns
13 ns
S1D13706
X31B-A-001-08