Table 4-5: Clock Input Pin Descriptions; Table 4-6: Miscellaneous Pin Descriptions; Table 4-7: Power And Ground Pin Descriptions - Epson S1D13706 Technical Manual

Page 28
4.4.3 Clock Input
Pin Name Type Pin #
CLKI I 15
CLKI2 I 77
4.4.4 Miscellaneous
Pin Name Type Pin #
CNF[7:0] I 78-85
GPO O 47
TESTEN I 86
4.4.5 Power And Ground
Pin Name Type Pin #
HIOVDD P 16, 26
37, 49,
NIOVDD P
63, 76
COREVDD P 1, 51
14, 25,
36, 50,
VSS P
62, 75,
100
S1D13706
X31B-A-001-08

Table 4-5: Clock Input Pin Descriptions

IO RESET#
Cell
Voltage State
LI NIOVDD —
LI NIOVDD —

Table 4-6: Miscellaneous Pin Descriptions

IO RESET#
Cell
Voltage State
LI NIOVDD —
LO3 NIOVDD 0
T1 NIOVDD 0

Table 4-7: Power And Ground Pin Descriptions

IO RESET#
Cell
Voltage State
P — —
P — —
P — —
P — —
Typically used as input clock source for bus clock and memory
clock
Typically used as input clock source for pixel clock
These inputs are used to configure the S1D13706 - see Table 4-8:
"Summary of Power-On/Reset Options," on page 29.
Note: These pins are used for configuration of the S1D13706
and must be connected directly to IO V
General Purpose Output (possibly used for controlling the LCD
power). It may also be used for the MOD control signal of the Sharp
HR-TFT panel.
Test Enable input used for production test only (has type 1 pull-
down resistor with a typical value of 50Ω at 3.3V).
IO V pins associated with the host interface pins as described in
DD
Section 4.4.1, "Host Interface" on page 22.
IO V pins associated with the non-host interface pins as
DD
described in Section 4.4.2, "LCD Interface" on page 26, Section
4.4.3, "Clock Input" on page 28, and Section 4.4.4, "Miscellaneous"
on page 28.
2 Core V pins.
DD.
7 V pins.
SS
Epson Research and Development
Vancouver Design Center
Description
Description
or V .
DD SS
Description
Hardware Functional Specification
Issue Date: 01/11/13