Lcd Pin Mapping For Y Connector (Lf37Sqt) - Epson S1D13706 Technical Manual

Page 16

3.2 LCD Pin Mapping for Y Connector (LF37SQT)

Table 3-2: LCD Pin Mapping for Y Connector: Pins for Y - Driver (LF37SQT)
LCD Pin LCD Pin S1D13706
No. Name Pin Name
Y-1 GND VSS (GND)
Y-2 SHF
Y-3 XINH GPIO0
Y-4 YSCL GPIO1
Y-5 FRY GPIO2
Y-6 VCCY
Y-7 V5Y
Y-8 NC
Y-9 V0Y
Y-10 VDD
Y-11 DYIO2 No Connect Start pulse signal
Y-12 DYIO1 FPFRAME
S1D13706
X31B-G-012-03
Description
Ground and power supply for liquid crystal
drive
- Shift direction selection for shift registers
Thinning control signal
Shift clock signal
AC signal for output
- Power supply for logic high
Power supply for logic low and liquid crystal
-
drive
- No Connect
- Power supply for liquid crystal drive
- Power supply for liquid crystal drive
Start pulse signal
Epson Research and Development
Vancouver Design Center
Remarks
Forward scanning: V5Y
Reverse scanning: VCCY
Connect to VCCY.
See Section 2.5, "Level Shift and Clamp
Circuit for Vertical Logic Control Signals"
on page 13.
See Section 2.5, "Level Shift and Clamp
Circuit for Vertical Logic Control Signals"
on page 13.
See Section 2.5, "Level Shift and Clamp
Circuit for Vertical Logic Control Signals"
on page 13.
See Section 2.4, "Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages" on page 12.
See Section 2.4, "Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages" on page 12.
See Section 2.4, "Swing Power Supply for
the Vertical Drive (V0Y) and Logic (VCCY
/ V5Y) Voltages" on page 12.
See Section 2.1, "VDDH and VDD -
Horizontal and Vertical Analog Voltages"
on page 8.
Forward scanning: Active low pulse
Reverse scanning: Open
Forward scanning: Open
Reverse scanning: Active low pulse
See Section 2.5, "Level Shift and Clamp
Circuit for Vertical Logic Control Signals"
on page 13.
Connecting to the Epson D-TFD Panels
Issue Date: 01/02/23