Table 6-12: Motorola Dragonball Interface With Dtack Timing - Epson S1D13706 Technical Manual

Epson Research and Development
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Symbol
f Bus Clock frequency
CLKO
T Bus Clock period
CLKO
t1 Clock pulse width high
t2 Clock pulse width low
A[16:1] setup 1st CLKO when CSX = 0 and either
t3
UWE/LWE or OE = 0
t4 A[16:1] hold from CSX rising edge
t5a CSX asserted for MCLK = BCLK
CSX asserted for MCLK = BCLK ÷ 2
t5b
CSX asserted for MCLK = BCLK ÷ 3
t5c
CSX asserted for MCLK = BCLK ÷ 4
t5d
t6 CSX setup to CLKO rising edge
t7 CSX rising edge to CLKO rising edge
t8 UWE/LWE falling edge to CLKO rising edge
t9 UWE/LWE rising edge to CSX rising edge
t10 OE falling edge to CLKO rising edge
t11 OE hold from CSX rising edge
D[15:0] setup to 3rd CLKO when CSX,
t12
UWE/LWE asserted (write cycle) (see note 1)
t13 D[15:0] in hold from CSX rising edge (write cycle)
t14 Falling edge of OE to D[15:0] driven (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
t15
(read cycle)
t16 CSX falling edge to DTACK driven high
t17 DTACK falling edge to D[15:0] valid (read cycle)
t18 CSX high to DTACK high
t19 CLKO rising edge to DTACK Hi-Z
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-12: Motorola DragonBall Interface with DTACK Timing

Parameter
MC68EZ328
2.0V 3.3V
Min Max Min Max
16 16
1/f 1/f
CLKO CLKO
28.1 28.1
28.1 28.1
0 0
0 0
8 8
11 11
13 13
17 17
0 0
0 0
1 0
0 0
1 1
0 0
1 0
0 0
4 30 3 15
4 21 2 12
3 20 3 13
0 2
5 34 3 16
5 40 1 6
MC68VZ328
2.0V 3.3V
Min Max Min Max
20 33
1/f 1/f
CLKO CLKO
22.5 13.5
22.5 13.5
0 0
0 0
8 8
11 11
13 13
17 17
0 0
0 0
1 0
0 0
1 1
0 0
1 0
0 0
4 30 3 15
4 21 2 12
3 20 3 13
0 2
5 34 3 16
5 40 1 6
S1D13706
X31B-A-001-08
Page 51
Unit
MHz
ns
ns
ns
ns
ns
T
CLKO
T
CLKO
T
CLKO
T
CLKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns