Single Color 8-Bit Panel Timing (Format 2); Figure 6-23: Single Color 8-Bit Panel Timing (Format 2) - Epson S1D13706 Technical Manual

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6.4.6 Single Color 8-Bit Panel Timing (Format 2)

FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
Invalid
FPDAT6
Invalid
FPDAT5
Invalid
FPDAT4
Invalid
FPDAT3
Invalid
FPDAT2
Invalid
FPDAT1 Invalid
FPDAT0 Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
VDP = Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-08
Invalid LINE1 LINE2 LINE3
2Ts Ts 2Ts 2Ts Ts
Ts Ts Ts Ts
1-R1 1-B3 1-G6
1-G1 1-R4 1-B6
1-B1 1-G4 1-R7
1-R2 1-B4 1-G7
1-G2 1-R5 1-B7
1-B2 1-G 5 1-R8
1-R3 1-B5 1-G8
1-G3 1-R6 1-B8

Figure 6-23: Single Color 8-Bit Panel Timing (Format 2)

VDP
LINE4 LINE239 LINE240
HDP
2Ts 2Ts Ts
Ts Ts
Epson Research and Development
Vancouver Design Center
VNDP
LINE1 LINE2
Invalid
HNDP
2Ts
Ts Ts
1-G318
Invalid
1-B318
Invalid
1-R319
Invalid
1-G319
Invalid
1-B319
Invalid
1-R320
Invalid
1-G320
Invalid
1-B320 Invalid
Hardware Functional Specification
Issue Date: 01/11/13