Toshiba Tmpr3905/12 To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

Embedded memory lcd controller

Hide thumbs Also See for S1D13706:

Table of Contents

4 Toshiba TMPR3905/12 to S1D13706 Interface

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

X31B-G-002-02

In this implementation, the S1D13706 occupies the TMPR3905/12 PC Card slot #1 IO

address space. IO address space closely matches the timing parameters for the S1D13706

Generic #2 Host Bus Interface.

The address bus of the TMPR3905/12 PC Card interface is multiplexed and must be demul-

tiplexed using an advanced CMOS latch (e.g., 74AHC373).

BS# (bus start) and RD/WR# are not used in this implementation and should be tied high

(connected to HIO V

A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.

The following diagram demonstrates a typical implementation of the TMPR3905/12 to

S1D13706 interface.

Clock divider

Figure 4-1: S1D13706 to TMPR3905/12 Direct Connection

System RESET

Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors

Epson Research and Development

Vancouver Design Center

Issue Date: 01/02/23

Table of Contents