Epson S1D13706 Technical Manual page 31

Epson Research and Development
Vancouver Design Center
Pin Name Type Pin #
WAIT# O 17
RESET# I 13
Hardware Functional Specification
Issue Date: 01/11/13
Table 4-3: Host Interface Pin Descriptions
IO RESET#
Cell
Voltage State
LB2A HIOVDD Hi-Z
LIS HIOVDD 0
During a data transfer, this output pin is driven active to force the
system to insert wait states. It is driven inactive to indicate the
completion of a data transfer. WAIT# is released to the high
impedance state after the data transfer is complete. Its active
polarity is configurable. See Table 4-8: "Summary of Power-
On/Reset Options," on page 29.
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
• For SH-4 mode, this pin outputs the device ready signal
(RDY#).
• For MC68K #1, this pin outputs the data transfer acknowledge
signal (DTACK#).
• For MC68K #2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer acknowledge
signal (DTACK).
See Table 4-9: "Host Bus Interface Pin Mapping," on page 30 for
summary.
Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
Description
X31B-A-001-08
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S1D13706