Interfacing To The Strongarm Sa-1110 Bus; The Strongarm Sa-1110 System Bus; Strongarm Sa-1110 Overview; Variable-Latency Io Access Overview - Epson S1D13706 Technical Manual

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2 Interfacing to the StrongARM SA-1110 Bus

2.1 The StrongARM SA-1110 System Bus

2.1.1 StrongARM SA-1110 Overview

2.1.2 Variable-Latency IO Access Overview

S1D13706
X31B-G-019-02
The StrongARM SA-1110 microprocessor is a highly integrated communications micro-
controller that incorporates a 32-bit StrongARM RISC processor core. The SA-1110 is
ideally suited to interface to the S1D13706 LCD controller and provides a high perfor-
mance, power efficient solution for embedded systems.
The SA-1110 system bus can access both variable-latency IO and memory devices. The
SA-1110 uses a 26-bit address bus and a 32-bit data bus which can be used to access 16-bit
devices. A chip select module with six chip select signals (each accessing 64M bytes of
memory) allows selection of external devices. Only chip selects 3 through 5 (nCS[5:3])
may be used to select variable-latency devices which use RDY to extend access cycles.
These chip selects are individually programmed in the SA-1110 memory configuration
registers and can be configured for either a 16 or 32-bit data bus.
Byte steering is implemented using the four signals nCAS[3:0]. Each signal selects a byte
on the 32-bit data bus. For example, nCAS0 selects bits D[7:0] and nCAS3 selects bits
D[31:24]. For a 16-bit data bus, only nCAS[1:0] are used with nCAS0 selecting the low
byte and nCAS1 selecting the high byte. The SA-1110 can be configured to support little
or big endian mode.
A data transfer is initiated when a memory address is placed on the SA-1110 system bus
and a chip select signal (nCS[5:3]) is driven low. If all byte enable signals (nCAS[3:0]) are
driven low, then a 32-bit transfer takes place. If only nCAS[1:0] are driven low, then a word
transfer takes place through a 16-bit bus interface. If only one byte enable is driven low,
then a byte transfer takes place on the respective data lines.
During a read cycle, the output enable signal (nOE) is driven low. A write cycle is specified
by driving nOE high and driving the write enable signal (nWE) low. The cycle can be
lengthened by driving RDY high for the time needed to complete the cycle.
Epson Research and Development
Interfacing to the Intel StrongARM SA-1110 Microprocessor
Vancouver Design Center
Issue Date: 02/06/26