Table 6-6: Generic #2 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Bus Clock frequency
BUSCLK
T Bus Clock period
BUSCLK
t1 Clock pulse width high
t2 Clock pulse width low
SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge
t3
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW#
t4
rising edge
t5 CS# setup to BUSCLK rising edge
t6 CS# hold from either MEMR# or MEMW# rising edge
t7a MEMR#/MEMW# asserted for MCLK = BCLK
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 2
t7b
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 3
t7c
MEMR#/MEMW# asserted for MCLK = BCLK ÷ 4
t7d
t8 MEMR# or MEMW# setup to BUSCLK rising edge
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
t9
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
t10
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
t11
MEMW# = 0 (write cycle) (see note 1)
t12 SD[15:0] hold from IOCHRDY rising edge (write cycle)
t13 MEMR# falling edge to SD[15:0] driven (read cycle)
t14 IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
t15
cycle)
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-6: Generic #2 Interface Timing

Parameter
2.0V
Min Max Min
20
1/f 1/f
BUSCLK BUSCLK
22.5 9
22.5 9
1 1
0 0
0 1
0 0
8.5
11.5
13.5
17.5
2 1
5 3
5 3
1 0
1 0
4 26 3
0
5 33 3
Page 39
3.3V
Unit
Max
50 MHz
ns
ns
ns
ns
ns
ns
ns
8 T
BUSCLK
11 T
BUSCLK
13 T
BUSCLK
17 T
BUSCLK
ns
15 ns
13 ns
ns
ns
13 ns
2 ns
12 ns
S1D13706
X31B-A-001-08