Epson S1D13706 Technical Manual page 615

Embedded memory lcd controller

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Table of Contents

Epson Research and Development

Vancouver Design Center

Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 12

Figure 4-1: Typical Implementation of 8-bit Processor to S1D13706 Interface . . . . . . . . . . . . 11

Interfacing to 8-bit Processors

Issue Date: 01/02/23

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List of Figures

X31B-G-015-02

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