Hr-Tft Mod Signal - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

2.2 HR-TFT MOD Signal

GPIOx*
(VSHD power)
GPIOy**
(other power)
GPO (MOD)
Power Save
Mode Enable***
(REG[A0h] bit 0)
LCD Signals****
*It is recommended to use one of the general purpose IO pins GPIO[6:4] to control the digital power supply VSHD.
** It is recommended to use one of the general purpose IO pins GPIO[6:4] to control the other power supplies required
by the HR-TFT panel.
***The S1D13706 LCD power-on/off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0
****LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and GPIO[3:0].
Symbol
t1
LCD Power (VSHD) active to Power Save Mode disabled
t2
LCD signals low to LCD Power (VSHD) inactive
t3
Power Save Mode disabled to LCD Power (other) active
t4
LCD Power (other) inactive to Power Save Mode enabled
t5
LCD Power (other) active to MOD active
t6
MOD inactive to LCD Power (other) inactive
t7
Power Save Mode disabled to LCD signals active
t8
Power Save Mode enabled to LCD signals low
Connecting to the Sharp HR-TFT Panels
Issue Date: 01/02/23
The HR-TFT panel uses an input signal (MOD) to control the power-on sequencing of the
panel. This HR-TFT signal should not be confused with the S1D13706 signal DRDY
(referred to as MOD for passive panels).
To power-on the HR-TFT panel, MOD must be held low until the power supply has been
turned on for more than two FRAMES. To power-off the HR-TFT panel, MOD must be
forced low before the power supply is turned off. This sequencing requires two software
controlled GPIO pins from the S1D13706 (see Figure 2-4: "HR-TFT Power-On/Off
Sequence Timing" ).
t1
t3
t7
Figure 2-4: HR-TFT Power-On/Off Sequence Timing
Table 2-1: HR-TFT Power-On/Off Sequence Timing
Parameter
t5
Active
t2
t4
t6
t8
Min Max
0
0
0
0
2
0
20
20
X31B-G-011-04
Page 11
Units
ns
ns
ns
ns
FRAME
ns
ns
ns
S1D13706