Register/Memory Mapping; Mc68Vz328 Chip Select And Pin Configuration - Epson S1D13706 Technical Manual

Epson Research and Development
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4.2.1 Register/Memory Mapping

4.2.2 MC68VZ328 Chip Select and Pin Configuration

Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor
Issue Date: 01/02/26
The S1D13706 requires two 128K byte segments in memory for the display buffer and its
internal registers. To accommodate this block size, it is preferable (but not required) to use
one of the chip selects from groups A or B. Groups A and B can have a size range of 128K
bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes.
Therefore, any chip select other than CSA0 would be suitable for the S1D13706 interface.
In the example interface, chip select CSB1 controls the S1D13706. A 256K byte address
space is used with the S1D13706 internal registers occupying the first 128K byte block and
the 80K byte display buffer located in the second 128K byte block. A17 from the
MC68VZ328 is used to select between these two 128K byte blocks.
The chip select used to map the S1D13706 (in this example CSB1) must have its RO (Read
Only) bit set to 0, its BSW (Bus Data Width) set to 1 for a 16-bit bus, and the WS (Wait
states) bits should be set to 111b to allow the S1D13706 to terminate bus cycles externally
with DTACK. The DTACK pin function must be enabled with Register FFFFF433, Port G
Select Register, bit 0.
If DTACK is not used, then the the WS bits should be set to either 4, 6, 10, or 12 software
wait states depending on the divide ratio between the S1D13706 MCLK and BCLK. The
WS bits should be set as follows.
S1D13706 MCLK to BCLK Divide Ratio
MCLK = BCLK ÷ 2
MCLK = BCLK ÷ 3
MCLK = BCLK ÷ 4
Table 4-3: WS Bit Programming
MCLK = BCLK
Page 13
WS Bits (wait states)
4
6
10
12
S1D13706
X31B-G-016-02