Table 6-5: Generic #1 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Bus Clock frequency
CLK
T Bus Clock period
CLK
t1 Clock pulse width high
t2 Clock pulse width low
A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and
t3
either RD0#, RD1# = 0 or WE0#, WE1# = 0
A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1#
t4
rising edge
t5 CS# setup to CLK rising edge
t6 CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
t7a RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
t7b RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
t7c RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
t7d RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
t8 RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
t9
driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
t10
high impedance
D[15:0] setup to third CLK rising edge where CS# = 0 and
t11
WE0#, WE1# = 0 (write cycle) (see note 1)
t12 D[15:0] hold from WAIT# rising edge (write cycle)
t13 RD0#, RD1# falling edge to D[15:0] driven (read cycle)
t14 WAIT# rising edge to D[15:0] valid (read cycle)
t15 RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-5: Generic #1 Interface Timing

Parameter
2.0V
Min Max
20
1/f
CLK
22.5
22.5
1
0
0
0
8.5
÷ 2
11.5
÷ 3
13.5
÷ 4
17.5
2
5 31
5 34
1
1
4 27
0
3 29
Page 37
3.3V
Unit
Min Max
50 MHz
1/f ns
CLK
9 ns
9 ns
1 ns
0 ns
1 ns
0 ns
8.5 T
CLK
11.5 T
CLK
13.5 T
CLK
17.5 T
CLK
1 ns
3 15 ns
3 13 ns
0 ns
0 ns
3 14 ns
2 ns
3 11 ns
S1D13706
X31B-A-001-08