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Main Window Line Address Offset Register 0
REG[78h]
7
6
Main Window Line Address Offset Register 1
REG[79h]
7
6
bits 9-0
S1D13706
X31B-A-001-08
Main window Line Address Offset Bits 7-0
5
n/a
5
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in DWORDS, from the beginning of one display line to
the beginning of the next display line in the main window. Note that this is a 32-bit
address increment. Calculate the Line Address Offset as follows:
Main Window Line Address Offset bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than the
display width and the displayed image becomes a window into the larger virtual image.
4
3
4
3
Epson Research and Development
Vancouver Design Center
Read/Write
2
1
Read/Write
Main window Line Address
Offset Bits 9-8
2
1
Hardware Functional Specification
Issue Date: 01/11/13
0
0
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