Motorola Mc68030 Bus Interface; Overview; Dynamic Bus Sizing; Asynchronous / Synchronous Bus Operation - Epson S1D13706 Technical Manual

Page 8

2 Motorola MC68030 Bus Interface

2.1 Overview

2.2 Dynamic Bus Sizing

2.3 Asynchronous / Synchronous Bus Operation

S1D13706
X31B-G-013-02
The MC68030 is a second generation enhanced microprocessor from the Motorola M68000
family of devices. The MC68030 is a 32-bit microprocessor with a 32-bit address bus and
a 32-bit data bus. The microprocessor supports both asynchronous and synchronous bus
cycles and burst data transfers. The bus also supports dynamic bus sizing which automati-
cally determines device port size on a cycle-by-cycle basis.
The MC68030 supports dynamic bus sizing using the following signals.
• SIZ1 and SIZ0 indicate the number of bytes remaining to be transfered for the current
bus cycle.
Table 2-1: SIZ Signal Encoding
SIZ1 SIZ0
0
1
1
0
• DSACK1 and DSACK0 (the data transfer size acknowledge signals) indicate the size of
the external port and acknowledge the end of the cycle.
Table 2-2: DSACK Decoding
DSACK1 DSACK0
1 1 Insert Wait States in the Current Bus Cycle
1 0 Complete Cycle - Data Bus Port Size is 8 bits
0 1 Complete Cycle - Data Bus Port Size is 16 bits
0 0 Complete Cycle - Data Bus Port Size is 32 bits
• A0 and A1 determine which portion of the data bus the data is transferred on and
whether the address is misaligned.
The MC68030 bus can operate asynchronously or synchronously. Asynchronous operation
requires DSACK0, DSACK1, AS, and DS to control transfers. The DSACK signals
specify the port width and insert wait states in the current bus cycle. AS (the address strobe)
Bytes Remaining
1 1 Byte
0 2 Bytes (Word)
1 3 Bytes
0 4 Bytes (Double Word)
Result
Interfacing to the Motorola MC68030 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/23