Features; Integrated Frame Buffer - Epson S1D13706 Technical Manual

Embedded memory lcd controller

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2 Features

2.2 CPU Interface

2.3 Display Support

X31B-A-001-08

• Embedded 80K byte SRAM display buffer.

• Direct support of the following interfaces:

Generic MPU bus interface using WAIT# signal.

Hitachi SH-3.

Hitachi SH-4.

Motorola M68K.

Motorola MC68EZ328/MC68VZ328 DragonBall.

Motorola "REDCAP2" - no WAIT# signal.

• 8-bit processor support with "glue logic".

• "Fixed" low-latency CPU access times.

• Registers are memory-mapped - M/R# input selects between memory and register

address space.

• The complete 80K byte display buffer is directly and contiguously available through the

17-bit address bus.

• Single level CPU write buffer.

• Single-panel, single-drive passive displays.

• 4/8-bit monochrome LCD interface.

• 4/8/16-bit color LCD interface.

• Active Matrix TFT interface.

• 9/12/18-bit interface.

• 'Direct' support for 18-bit Epson D-TFD interface.

• 'Direct' support for 18-bit Sharp HR-TFT interface.

Epson Research and Development

Vancouver Design Center

Hardware Functional Specification

Issue Date: 01/11/13

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