Registers; Power Save Mode Enable; Memory Controller Power Save Status - Epson S1D13706 Technical Manual

Epson Research and Development
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5.2 Registers

5.2.1 Power Save Mode Enable

REG[A0h] Power Save Configuration Register
VNDP Status
n/a
(RO)
Note

5.2.2 Memory Controller Power Save Status

REG[A0h] Power Save Configuration Register
VNDP Status
n/a
(RO)
Note
Programming Notes and Examples
Issue Date: 01/02/23
n/a
The Power Save Mode Enable bit initiates Power Save Mode when set to 1. Setting the bit
back to 0 returns the S1D13706 back to normal mode.
Enabling/disabling Power Save Mode requires proper LCD Power Sequencing. See Sec-
tion 6, "LCD Power Sequencing" on page 29.
n/a
The Memory Controller Power Save Status bit is a read-only status bit which indicates the
power save state of the S1D13706 SRAM interface. When this bit returns a 1, the SRAM
interface is powered down. When this bit returns a 0, the SRAM interface is active. This bit
returns a 0 after a chip reset.
The memory clock source may be disabled when this bit returns a 1.
Memory
Controller
n/a
Power Save
Status (RO)
Memory
Controller
n/a
Power Save
Status (RO)
Read/Write
n/a n/a
Mode Enable
Read/Write
n/a n/a
Mode Enable
Page 27
Power Save
Power Save
S1D13706
X31B-G-003-03