Table 8-3: Pclk Divide Selection; Table 8-4: Pclk Source Selection - Epson S1D13706 Technical Manual

Page 98
Pixel Clock Configuration Register
REG[05h]
n/a PCLK Divide Select Bits 2-0
7 6
bits 6-4
bits 1-0
S1D13706
X31B-A-001-08
5
PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.

Table 8-3: PCLK Divide Selection

PCLK Divide Select Bits
000
001
010
011
1XX
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).

Table 8-4: PCLK Source Selection

PCLK Source Select Bits
00
01
10
11
n/a
4 3
PCLK Source to PCLK Frequency Ratio
Epson Research and Development
Vancouver Design Center
Read/Write
PCLK Source Select Bits 1-0
2 1
1:1
2:1
3:1
4:1
8:1
PCLK Source
MCLK
BCLK
CLKI
CLKI2
Hardware Functional Specification
Issue Date: 01/11/13
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