Power Save Mode; Overview - Epson S1D13706 Technical Manual

Embedded memory lcd controller

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5 Power Save Mode

X31B-G-003-03

The S1D13706 is designed for very low-power applications. During normal operation, the

internal clocks are dynamically disabled when not required. The S1D13706 design also

includes a Power Save Mode to further save power. When Power Save Mode is initiated,

LCD power sequencing is required to ensure the LCD bias power supply is disabled

properly. For further information on LCD power sequencing, see Section 6, "LCD Power

Sequencing" on page 29.

For Power Save Mode AC Timing, see the S1D13706 Hardware Functional Specification,

document number X31B-A-001-xx.

The S1D13706 includes a software initiated Power Save Mode. Enabling/disabling Power

Save Mode is controlled using the Power Save Mode Enable bit (REG[A0h] bit 0).

While Power Save Mode is enabled the following conditions apply.

• LCD display is inactive.

• LCD interface outputs are forced low.

• Memory is in-accessible.

• Registers are accessible.

• Look-Up Table registers are accessible.

Epson Research and Development

Vancouver Design Center

Programming Notes and Examples

Issue Date: 01/02/23

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