Table 6-2: Clock Input Requirements For Clki When Clki To Bclk Divide = 1; Table 6-3: Clock Input Requirements For Clki2 - Epson S1D13706 Technical Manual

Page 34

Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1

Symbol
f Input Clock Frequency (CLKI)
OSC
T Input Clock period (CLKI)
OSC
t Input Clock Pulse Width High (CLKI)
PWH
t Input Clock Pulse Width Low (CLKI)
PWL
t Input Clock Fall Time (10% - 90%)
f
t Input Clock Rise Time (10% - 90%)
r
Symbol
f Input Clock Frequency (CLKI2)
OSC
T Input Clock period (CLKI2)
OSC
t Input Clock Pulse Width High (CLKI2)
PWH
t Input Clock Pulse Width Low (CLKI2)
PWL
t Input Clock Fall Time (10% - 90%)
f
t Input Clock Rise Time (10% - 90%)
r
S1D13706
X31B-A-001-08
Parameter
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, "Internal Clocks" on page
35 for internal clock requirements.

Table 6-3: Clock Input Requirements for CLKI2

Parameter
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered
when determining the frequency of CLKI2. See Section 6.1.2, "Internal Clocks" on page
35 for internal clock requirements.
Epson Research and Development
Vancouver Design Center
2.0V 3.3V
Min Max Min
20
1/f 1/f
OSC OSC
3 3
3 3
5
5
2.0V 3.3V
Min Max Min
20
1/f 1/f
OSC OSC
3 3
3 3
5
5
Hardware Functional Specification
Units
Max
66 MHz
ns
ns
ns
5 ns
5 ns
Units
Max
66 MHz
ns
ns
ns
5 ns
5 ns
Issue Date: 01/11/13