Table 8-15: Pwm Clock Control; Figure 8-2: Pwm Clock/Cv Pulse Block Diagram; Pulse Width Modulation (Pwm) Clock And Contrast Voltage (Cv) Pulse Configuration Registers - Epson S1D13706 Technical Manual

Page 126
8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse
Configuration Registers
PWMCLK
m = PWM Clock Divide Select value
x = CV Pulse Divide Select value
PWM Clock / CV Pulse Control Register
REG[B0h]
PWM Clock
Force High
7 6
bit 7 and bit 4
Bit 7
0
0
1
x = don't care
S1D13706
X31B-A-001-08
Divided
PWM Clock
Clock
Divider
m
Clock Source / 2
Divided
CV Pulse
Clock
Divider
x
Clock Source / 2

Figure 8-2: PWM Clock/CV Pulse Block Diagram

Note
For further information on PWMCLK, see Section 7.1.4, "PWMCLK" on page 92.
PWM Clock
n/a
Enable
5
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the PWMOUT pin and PWM Clock circuitry as follows.

Table 8-15: PWM Clock Control

Bit 4
1
0
x
When PWMOUT is forced low or forced high it can be used as a general purpose output.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
PWM Clock Enable
PWM Duty Cycle
Modulation
Duty = n / 256
n = PWM Clock Duty Cycle
PWM Clock Force High
CV Pulse Enable
CV Pulse Burst
Generation
y-pulse burst
y = Burst Length value
CV Pulse Force High
CV Pulse
Burst Status
Force High
4 3
PWM Clock circuitry enabled
(controlled by REG[B1h] and REG[B3h])
PWMOUT forced low
PWMOUT forced high
Epson Research and Development
Vancouver Design Center
frequency =
Clock Source / (2
frequency =
Clock Source / (2
CV Pulse
CV Pulse
Burst Start
(RO)
2 1
Result
Hardware Functional Specification
Issue Date: 01/11/13
to PWMOUT
m
X 256)
to CVOUT
x
X 2)
Read/Write
CV Pulse
Enable
0