Table 8-2: Mclk Divide Selection; Clock Configuration Registers - Epson S1D13706 Technical Manual

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Display Buffer Size Register
REG[01h]
7 6
bits 7-0
Configuration Readback Register
REG[02h]
CNF7 Status CNF6 Status CNF5 Status
7 6
bits 7-0

8.3.2 Clock Configuration Registers

Memory Clock Configuration Register
REG[04h]
n/a
7 6
bits 5-4
bit 0
Hardware Functional Specification
Issue Date: 01/11/13
Display Buffer Size Bits 7-0
5
Display Buffer Size Bits [7:0]
This is a read-only register that indicates the size of the SRAM display buffer measured in
4K byte increments. The S1D13706 display buffer is 80K bytes and therefore this register
returns a value of 20 (14h).
Value of this register = display buffer size ÷ 4K bytes
= 80K bytes ÷ 4K bytes
= 20 (14h)
CNF4 Status
5
CNF[7:0] Status
These read-only status bits return the status of the configuration pins CNF[7:0]. CNF[7:0]
are latched at the rising edge of RESET#.
MCLK Divide Select Bits 1-0
5
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the Bus
Clock (BCLK).

Table 8-2: MCLK Divide Selection

MCLK Divide Select Bits
00
01
10
11
Reserved.
This bit must remain at 0.
4 3
CNF3 Status CNF2 Status
4 3
4 3
BCLK to MCLK Frequency Ratio
2 1
CNF1 Status CNF0 Status
2 1
Read/Write
n/a
2 1
1:1
2:1
3:1
4:1
Page 97
Read Only
0
Read Only
0
Reserved
0
S1D13706
X31B-A-001-08