Figure 6-15: Single Monochrome 4-Bit Panel Timing - Epson S1D13706 Technical Manual

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6.4.2 Single Monochrome 4-Bit Panel Timing
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
VDP = Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-08
Invalid LINE1 LINE2
Invalid 1-1 1-5
Invalid 1-2 1-6
Invalid
1-3
1-7
Invalid
1-4 1-8

Figure 6-15: Single Monochrome 4-Bit Panel Timing

VDP
LINE3 LINE4 LINE239 LINE240
HDP
Epson Research and Development
Vancouver Design Center
VNDP
LINE1 LINE2
Invalid
HNDP
1-317
Invalid
1-318 Invalid
1-319
Invalid
1-320
Invalid
Hardware Functional Specification
Issue Date: 01/11/13