Table 6-11: Motorola Redcap2 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f
Bus Clock frequency
CKO
T
Bus Clock period
CKO
t1
Bus Clock pulse width low
t2
Bus Clock pulse width high
t3
A[16:1], M/R#, R/W, CSn setup to CKO rising edge
t4
A[16:1], M/R#, R/W, CSn hold from CKO rising edge
t5a
CSn asserted for MCLK = BCLK
CSn asserted for MCLK = BCLK ÷ 2
t5b
CSn asserted for MCLK = BCLK ÷ 3
t5c
CSn asserted for MCLK = BCLK ÷ 4
t5d
t6
EB0, EB1 asserted to CKO rising edge (write cycle)
t7
EB0, EB1 de-asserted to CKO rising edge (write cycle)
D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1
t8
asserted low (write cycle) (see note 1)
D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1
t9
asserted low (write cycle)
t10
OE, EB0, EB1 setup to CKO rising edge (read cycle)
t11
OE, EB0, EB1 hold to CKO rising edge (read cycle)
D[15:0] output delay from OE, EB0, EB1 falling edge
t12
(read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
t13a
valid for MCLK = BCLK (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
t13b
valid for MCLK = BCLK ÷ 2 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
t13c
valid for MCLK = BCLK ÷ 3 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
t13d
valid for MCLK = BCLK ÷ 4 (read cycle)
t14
CKO rising edge to D[15:0] output in Hi-Z (read cycle)
1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-11: Motorola REDCAP2 Interface Timing

Parameter
2.0V 3.3V
Min Max Min
17
1/f 1/f
CKO CKO
26 26
26 26
1 1
0 0
8 8
10 10
13 13
15 15
1 1
1 4
1 0
23 8
1 0
1 0
4 29 3
4.5CKO
+ 7
7CKO +
10
8.5CKO
+ 8
9CKO +
11
4 31 1
Page 49
Units
Max
17 MHz
ns
ns
ns
ns
ns
T
CKO
T
CKO
T
CKO
T
CKO
ns
ns
ns
ns
ns
ns
10 ns
4.5CKO +
ns
20
6.5CKO +
ns
20
9.5CKO +
ns
20
11.5CKO
ns
+ 20
11 ns
S1D13706
X31B-A-001-08