Epson S1D13706 Technical Manual page 173

Embedded memory lcd controller

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Epson Research and Development

Vancouver Design Center

Programming Notes and Examples

Issue Date: 01/02/23

Table 2-1: Example Register Values (Continued)

GPIO[6:0] pins are driven low

Set the GPO control bit to low

PWM Clock and CV Pulse Configuration

Selects the following:

• PWMOUT pin is software controlled

• PWM Clock circuitry is disabled

• CVOUT pin is software controlled

• CV Pulse circuitry is disabled

Sets the PWM Clock and CV Pulse divides

Sets the CV Pulse Burst Length

Sets the PWMOUT signal to always low

Bit 7 controls the LCD bias

power for the panel on the

S5U13706B00C.

For this example the

divides are not required.

For this example, the burst

length is not required.

X31B-G-003-03

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