Epson S1D13706 Technical Manual page 131

Epson Research and Development
Vancouver Design Center
bit 0
General Purpose IO Pins Status/Control Register 1
REG[ADh]
GPO Control
7 6
bit 7
Note
Hardware Functional Specification
Issue Date: 01/11/13
GPIO0 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this bit
drives GPIO0 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is
configured as an input, a read from this bit returns the status of GPIO0.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO0 outputs the XINH sig-
nal automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO0 outputs the PS signal
automatically and writing to this bit has no effect.
5
GPO Control
This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives GPO to low.
Writing a 1 to this bit drives GPO to high.
Many implementations use the GPO pin to control the LCD bias power (see Section 6.3,
"LCD Power Sequencing" on page 54).
n/a
4 3
Read/Write
2 1
X31B-A-001-08
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S1D13706