Power-On/Off Sequence - Epson S1D13706 Technical Manual

Page 18

4 Power-On/Off Sequence

GPO*
Power Save
Mode Enable**
(REG[A0h] bit 0)
LCD Signals***
GPIO5 Pin IO
Status/Control
(REG[ACh] bit 5)
GPIO5 (DD_P1)
*It is recommended that LCD power be controlled using the general output pin GPO.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, DRDY, GPIO6, and GPIO[4:0].
Symbol
t1
LCD power active to LCD signals active
t2
Power Save Mode Enable bit low to LCD signals active
t3
Power Save Mode Enable bit high to LCD signals low
t4
LCD signals low to LCD power inactive
t5
LCD signals active to GPIO5 active
t6
GPIO5 Pin IO Status high to GPIO5 active
t7
GPIO5 Pin IO Status low to GPIO5 inactive
t8
GPIO5 inactive to LCD signals low
1. t1 and t 4 are controlled by software and must be determined from the timing requirements of the panel
connected.
S1D13706
X31B-G-012-03
The D-TFD panel requires a specific sequence to power-on/off. For further information on
power sequencing the D-TFD panel, see the specification for each specific panel.
t1
t2
Figure 4-1: D-TFD Power-On/Off Sequence Timing
Table 4-1: D-TFD Power-On/Off Sequence Timing
Parameter
Active
t5
t6
t7
Active
Epson Research and Development
Vancouver Design Center
t3 t4
t8
Min Max
Note 1
0 20
20
Note 1
2
20
20
3
Connecting to the Epson D-TFD Panels
Issue Date: 01/02/23
Units
ns
ns
FRAME
ns
ns
FRAME