Host Bus Interface Signals - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

3.2 Host Bus Interface Signals

Interfacing to the PC Card Bus
Issue Date: 01/02/23
The S1D13706 Generic #2 Host Bus Interface requires the following signals from the PC
Card bus.
• CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. Since the PC Card signalling is independent of any clock, CLKI can come
from any oscillator already implemented. For example, the source for the CLKI2 input
of the S1D13706 may be used.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the PC
Card address (A[16:0]) and data bus (D[15:0]), respectively. CNF4 must be set to select
little endian mode.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
register and memory address space.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A17 to be connected to the
M/R# line.
• WE1# is the high byte enable for both read and write cycles and connects to the PC Card
high byte chip select signal (-CE2).
• WE0# connects to -WE (the write enable signal form the PC Card bus) and must be
driven low when the PC Card bus is writing data to the S1D13706.
• RD# connects to -OE (the read enable signal from the PC Card bus) and must be driven
low when the PC Card bus is reading data from the S1D13706.
• WAIT# is a signal output from the S1D13706 that indicates the PC Card bus must wait
until data is ready (read cycle) or accepted (write cycle) on the host bus. Since PC Card
bus accesses to the S1D13706 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 13706 internal registers and/or
display buffer. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in this implemen-
tation of the PC Card bus using the Generic #2 Host Bus Interface. These pins must be
tied high (connected to HIO V
• The RESET# (active low) input of the S1D13706 may be connected to the PC Card
RESET (active high) using an inverter.
).
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