Clock Synthesizer And Clock Options; Clock Programming - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

7 Clock Synthesizer and Clock Options

Note

7.1 Clock Programming

Note
S5U13706B00C Rev. 1.0 Evaluation Board User Manual
Issue Date: 01/02/23
For maximum flexibility, the S5U13706B00C implements a Cypress ICD2061A Clock
Generator. MCLKOUT from the clock synthesizer is connected to CLKI2 of the S1D13706
and VCLKOUT from the clock synthesizer is connected to CLKI of the S1D13706. A
14.31818MHz crystal (Y1) is connected to XTALIN and XTALOUT of the clock synthe-
sizer.
Synthesizer reference
14.31818 MHz
Figure 7-1: Symbolic Clock Synthesizer Connections
At power-on, CLKI2 (MCLKOUT) is configured to be 40MHz and CLKI (VCLKOUT) is
configured at 25.175MHz.
If an Epson D-TFD panel is selected, the clock synthesizer cannot be programmed, and
external oscillators must provide the clock signals to CLKI and CLKI2. Jumpers JP2
and JP3 allow selection of external oscillators U5 and U6 as the clock source for both
CLKI and CLKI2. For further information, see Table 3-2: "Jumper Summary" on page
11.
The S1D13706 utilities automatically program the clock generator. If manual programming
of the clock generator is required, refer to the source code for the S1D13706 utilities
available on the internet at www.eea.epson.com.
For further information on programming the clock generator, refer to the Cypress
ICD2061A specification.
When CLKI and CLKI2 are programmed to multiples of each other (e.g. CLKI =
20MHz, CLKI2 = 40MHz), the clock output signals from the Cypress clock generator
may jitter. Refer to the Cypress ICD2061A specification for details.
To avoid this problem, set CLKI and CLKI2 to different frequencies use the S1D13706
internal clock divides to obtain the lower frequencies.
ICD2061A
XTALIN MCLKOUT
VCLKOUT
Page 23
CLKI2
CLKI
S1D13706
X31B-G-004-04