Epson S1D13706 Technical Manual page 259

S1D13706 Register Summary S1D13706 Register Summary
1
REG[00h] R EVISION C ODE R EGISTER
Product Code = 001010
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[01h] D B S R
ISPLAY UFFER IZE EGISTER
Display Buffer Size
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
REG[02h] C R R
ONFIGURATION EADBACK EGISTER
CNF7 Status CNF6 Status CNF5 Status CNF4 Status CNF3 Status CNF2 Status CNF1 Status CNF0 Status
2
REG[04h] M EMORY C LOCK C ONFIGURATION R EGISTER
MCLK Divide Select
n/a n/a n/a
bit 1 bit 0
EGISTER 3,4
REG[05h] P C C R
IXEL LOCK ONFIGURATION
PCLK Divide Select
n/a n/a
Bit 2 Bit 1 Bit 0
REG[08h] L -U T B W D R
OOK P ABLE LUE RITE ATA EGISTER
LUT Blue Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[09h] L -U T G W D R
OOK P ABLE REEN RITE ATA EGISTER
LUT Green Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[0Ah] L OOK -U P T ABLE R ED W RITE D ATA R EGISTER
LUT Red Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[0Bh] L -U T W A R
OOK P ABLE RITE DDRESS EGISTER
LUT Write Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
REG[0Ch] L -U T B R D R
OOK P ABLE LUE EAD ATA EGISTER
LUT Blue Read Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[0Dh] L -U T G R D R
OOK P ABLE REEN EAD ATA EGISTER
LUT Green Read Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[0Eh] L OOK -U P T ABLE R ED R EAD D ATA R EGISTER
LUT Red Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
REG[0Fh] L -U T R A R
OOK P ABLE EAD DDRESS EGISTER
LUT Read Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
EGISTER 5,6
REG[10h] P T R
ANEL YPE
Panel Data Panel Data Width
Color/Mono Active Panel
Format
Panel Select Res. Select
Bit 1 Bit 0
Select
REG[11h] MOD R R
ATE EGISTER
MOD Rate
n/a n/a
bit 5 bit 4 bit 3
REG[12h] H T R
ORIZONTAL OTAL EGISTER
Horizontal Total
n/a
Bit 6 Bit 5 Bit 4 Bit 3
REG[14h] H D P R
ORIZONTAL ISPLAY ERIOD EGISTER
Horizontal Display Period
n/a
Bit 6 Bit 5 Bit 4 Bit 3
Page 1
RO REG[16h] H ORIZONTAL
Revision Code = 00
Bit 0 Bit 1 Bit 0 bit 7 bit 6
RW REG[17h] H
ORIZONTAL
n/a n/a
Bit 2 Bit 1 Bit 0
RO
REG[18h] V T
ERTICAL
Bit 7 Bit 6
RW
Reserved
n/a n/a
REG[19h] V T
ERTICAL
n/a n/a
RW
PCLK Source Select
n/a
REG[1Ch] V D
ERTICAL
Bit 1 Bit 0
Bit 7 Bit 6
WO
n/a n/a
REG[1Dh] V D
ERTICAL
Bit 0
n/a n/a
WO
n/a n/a
REG[1Eh] V D
ERTICAL
Bit 0
Bit 7 Bit 6
WO
n/a n/a
REG[1Fh] V D
ERTICAL
Bit 0
n/a n/a
WO
Bit 2 Bit 1 Bit 0
REG[20h] FPLINE P
ULSE
FPLINE
RO Pulse
Bit 6
Polarity
n/a n/a
Bit 0
REG[22h] FPLINE P
ULSE
RO
Bit 7 Bit 6
n/a n/a
Bit 0
REG[23h] FPLINE P
ULSE
RO
n/a n/a
n/a n/a
Bit 0
REG[24h] FPFRAME P
WO
FPFRAME
Pulse n/a
Polarity
Bit 2 Bit 1 Bit 0
REG[26h] FPFRAME P
RW
Panel Type
Bit 7 Bit 6
n/a
Bit 1 Bit 0
REG[27h] FPFRAME P
RW
n/a n/a
bit 2 bit1 bit 0
REG[28h] D-TFD GCP I
RW
n/a n/a
Bit 2 Bit 1 Bit 0
REG[2Ch] D-TFD GCP D
RW
Bit 7 Bit 6
Bit 2 Bit 1 Bit 0
D ISPLAY P ERIOD S TART P OSITION R EGISTER 0
Horizontal Display Period Start Position
bit 5 bit 4 bit 3 bit 2 bit 1
D P S P R 1
ISPLAY ERIOD TART OSITION EGISTER
Horizontal Display Period
n/a n/a n/a n/a
bit 9
R 0
OTAL EGISTER
Vertical Total
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
R 1
OTAL EGISTER
n/a n/a n/a n/a
Bit 9
P R 0
ISPLAY ERIOD EGISTER
Vertical Display Period
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
P R 1
ISPLAY ERIOD EGISTER
Vertical Display Period
n/a n/a n/a n/a
Bit 9
P S P R 0
ISPLAY ERIOD TART OSITION EGISTER
Vertical Display Period Start Position
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
P S P R 1
ISPLAY ERIOD TART OSITION EGISTER
Vertical Display Period
n/a n/a n/a n/a
bit 9
W R
IDTH EGISTER
FPLINE Pulse Width
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
S P R 0
TART OSITION EGISTER
FPLINE Pulse Start Position
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
S P R 1
TART OSITION EGISTER
FPLINE Pulse Start
n/a n/a n/a n/a
Bit 9
W R
ULSE IDTH EGISTER
FPFRAME Pulse Width
n/a n/a n/a
Bit 2 Bit 1
S P R 0
ULSE TART OSITION EGISTER
FPFRAME Pulse Start Position
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
S P R 1
ULSE TART OSITION EGISTER
FPFRAME Pulse Start
n/a n/a n/a n/a
Bit 9
NDEX R EGISTER
D-TFD GCP Index
n/a
Bit 4 Bit 3 Bit 2 Bit 1
ATA R EGISTER
D-TFD GCP Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
7
RW REG[70h] D ISPLAY M ODE R EGISTER
Hardware
Display Dithering
Video Invert
bit 0 Blank Disable
Enable
RW
REG[71h] S E R
PECIAL FFECTS EGISTER
Display Data Display Data
Start Position
n/a
Word Swap Byte Swap
bit 8
REG[74h] M W D S
AIN INDOW ISPLAY TART
RW
Main Window Display Start Address
Bit 7 Bit 6 Bit 5
Bit 0
REG[75h] M W D S
AIN INDOW ISPLAY TART
RW
Main Window Display Start Address
Vertical Total
Bit 15 Bit 14 Bit 13
Bit 8
REG[76h] M W D S
AIN INDOW ISPLAY TART
RW
n/a n/a n/a
Bit 0
RW
REG[78h] M AIN W INDOW L INE A DDRESS
Bit 8
Main Window Line Address Offset
Bit 7 Bit 6 Bit 5
RW
REG[79h] M W L A
AIN INDOW INE DDRESS
Bit 0
n/a n/a n/a
RW
Start Position
REG[7Ch] S -W D S
UB INDOW ISPLAY TART
bit 8
Sub-Window Display Start Address
Bit 7 Bit 6 Bit 5
RW
REG[7Dh] S -W D S
UB INDOW ISPLAY TART
Bit 0 Sub-Window Display Start Address
Bit 15 Bit 14 Bit 13
RW
REG[7Eh] S -W D S
UB INDOW ISPLAY TART
Bit 0
n/a n/a n/a
RW
Position
REG[80h] S -W L A
UB INDOW INE DDRESS
Bit 8
Sub-Window Line Address Offset
Bit 7 Bit 6 Bit 5
RW
REG[81h] S -W L A
UB INDOW INE DDRESS
Bit 0
n/a n/a n/a
RW
REG[84h] S -W X S P
UB INDOW TART OSITION
Bit 0
Bit 7 Bit 6 Bit 5
RW
REG[85h] S UB -W INDOW X S TART P OSITION
Position
Bit 8
n/a n/a n/a
RW
REG[88h] S -W Y S P
UB INDOW TART OSITION
Bit 0
Bit 7 Bit 6 Bit 5
RW
Bit 0
X31B-R-001-02 X31B-R-001-02
RW
Bit-per-pixel Select
Software
n/a
Video Invert
Bit 2 Bit 1 Bit 0
8
RW
SwivelView™ Mode Select
Sub-Window
n/a n/a
Enable
Bit 1 Bit 0
A R 0 RW
DDRESS EGISTER
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A R 1 RW
DDRESS EGISTER
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
A R 2 RW
DDRESS EGISTER
Main
Window
n/a n/a n/a n/a Display Start
Address Bit
16
O FFSET R EGISTER 0 RW
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
O R 1 RW
FFSET EGISTER
Main Window Line
Address Offset
n/a n/a n/a
Bit 9 Bit 8
A R 0 RW
DDRESS EGISTER
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A R 1 RW
DDRESS EGISTER
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
A R 2 RW
DDRESS EGISTER
Sub-Window
Display Start
n/a n/a n/a n/a
Address Bit
16
O R 0 RW
FFSET EGISTER
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
O R 1 RW
FFSET EGISTER
Sub-Window Line Address
Offset
n/a n/a n/a
Bit 9 Bit 8
R 0 RW
EGISTER
Sub-Window X Start Position
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R EGISTER 1 RW
Sub-Window X Start
Position
n/a n/a n/a
Bit 9 Bit 8
R 0 RW
EGISTER
Sub-Window Y Start Position
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01/02/26