Table 4-8: Summary Of Power-On/Reset Options; Summary Of Configuration Options - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

4.5 Summary of Configuration Options

S1D13706
Configuration
Input
Select host bus interface as follows:
CNF4,CNF[2:0]
Note: The host bus interface is 16-bit only.
CNF3 Configure GPIO pins as inputs at power-on
CNF5 WAIT# is active high
CLKI to BCLK divide select:
CNF[7:6]
Hardware Functional Specification
Issue Date: 01/11/13
These pins are used for configuration of the S1D13706 and must be connected directly to
NIOV or V . The state of CNF[6:0] is latched on the rising edge of RESET#. Changing
DD SS
state at any other time has no effect.

Table 4-8: Summary of Power-On/Reset Options

1 (connected to NIOV
CNF4 CNF2 CNF1
1 0 0
0 0 0
1 0 0
0 0 0
1 0 1
0 0 1
1 0 1
0 0 1
1 1 0
0 1 0
1 1 0
0 1 0
1 1 1
0 1 1
X 1 1
CNF7 CNF6
0 0
0 1
1 0
1 1
Power-On/Reset State
)
DD
CNF0 Host Bus
0 SH-4/SH-3 interface, Big Endian
0 SH-4/SH-3 interface, Little Endian
1 MC68K #1, Big Endian
1 Reserved
0 MC68K #2, Big Endian
0 Reserved
1 Generic #1, Big Endian
1 Generic #1, Little Endian
0 Reserved
0 Generic #2, Little Endian
1 REDCAP2, Big Endian
1 Reserved
0 DragonBall (MC68EZ328/MC68VZ328), Big Endian
0 Reserved
1 Reserved
Configure GPIO pins as outputs at power-on (for use
by HR-TFT/D-TFD when selected)
WAIT# is active low
CLKI to BCLK Divide Ratio
1 : 1
2 : 1
3 : 1
4 : 1
0 (Connected to V )
SS
X31B-A-001-08
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S1D13706