Host Bus Interface Signals - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

3.2 Host Bus Interface Signals

Interfacing to the Motorola MC68030 Microprocessor
Issue Date: 01/02/23
The Host Bus Interface requires the following signals.
• CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. For this example, CLK from the Motorola MC68030 is used for CLKI.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the
MC68030 address (A[16:0) and data bus (D[31:16]), respectively. CNF4 must be set to
select big endian mode.
• Chip Select (CS#) must be driven low by the external address decode circuitry whenever
the S1D13706 is accessed by the Motorola MC68030.
• M/R# (memory/register) selects between memory or register accesses. This signal is
generated by the external address decode circuitry.
• WE0# connects to SIZ0, one of the transfer size signals of the MC68030. Along with
SIZ1 this signal indicates how many bytes are to be transferred during the current cycle.
• WE1# connects to DS (the data strobe signal from the MC68030) and must be driven
low when valid data has been placed on the bus.
• RD# connects to external decode circuitry of SIZ1, one of the transfer size signals of the
MC68030. Along with SIZ0 this signal indicates how many bytes are to be transferred
during the current cycle.
• RD/WR# is the read or write enable signal and connects to R/W of the MC68030. This
signal drives low when the MC68030 is writing to the S1D13706 and drives high when
the MC68030 is reading from the S1D13706.
• WAIT# connects to DSACK1 and is a signal which is output from the S1D13706 which
indicates the MC68030 must wait until data is ready (read cycle) or accepted (write
cycle) on the host bus. Since MC68030 accesses to the S1D13706 may occur asynchro-
nously to the display update, it is possible that contention may occur in accessing the
S1D13706 internal registers and/or display buffer. The WAIT# line resolves these
contentions by forcing the host to wait until the resource arbitration is complete.
• BS# connects to AS (the address strobe from the MC68030) and must be driven low
when a valid address has been placed on the address bus.
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