Epson S1D13706 Technical Manual page 260

S1D13706 Register Summary
REG[89h] S UB -W INDOW Y S TART P OSITION R EGISTER 1
n/a n/a n/a n/a n/a
REG[8Ch] S UB -W INDOW X E ND P OSITION R EGISTER 0
Sub-Window X End Position
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
REG[8Dh] S -W X E P R 1
UB INDOW ND OSITION EGISTER
n/a n/a n/a n/a n/a
REG[90h] S -W Y E P R 0
UB INDOW ND OSITION EGISTER
Sub-Window Y End Position
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
REG[91h] S -W Y E P R 1
UB INDOW ND OSITION EGISTER
n/a n/a n/a n/a n/a
REG[A0h] P S C R
OWER AVE ONFIGURATION EGISTER
Memory
VNDP Controller
n/a n/a n/a
Status (RO) Power Save
Status (RO)
REG[A1h] R
ESERVED
n/a n/a n/a n/a n/a
REG[A2h] S R R
OFTWARE ESET EGISTER
Reserved n/a n/a n/a n/a
REG[A3h] R
ESERVED
Reserved n/a n/a n/a n/a
REG[A4h] S P R 0
CRATCH AD EGISTER
Scratch Pad
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
REG[A5h] S P R 1
CRATCH AD EGISTER
Scratch Pad
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11
REG[A8h] G P IO P C R
ENERAL URPOSE INS ONFIGURATION EGISTER
GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin
n/a
IO Config IO Config IO Config IO Config
REG[A9h] G P IO P C R
ENERAL URPOSE INS ONFIGURATION EGISTER
GPIO Pin
Reserved Reserved Reserved Reserved
Input Enable
REG[ACh] G P IO P S /C R
ENERAL URPOSE INS TATUS ONTROL EGISTER
GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin
n/a
IO Status IO Status IO Status IO Status
REG[ADh] G P IO P S /C R
ENERAL URPOSE INS TATUS ONTROL EGISTER
GPO Control Reserved Reserved Reserved Reserved
REG[B0h] PWM C LOCK / CV P ULSE C ONTROL R EGISTER
PWM Clock PWM Clock CV Pulse
n/a n/a
Force High Enable Force High
EGISTER 9,10
REG[B1h] PWM C LOCK / CV P ULSE C ONFIGURATION R
PWM Clock Divide Select CV Pulse Divide Select
Bit 3 Bit 2 Bit 1 Bit 0 Bit 2
Page 2
RW REG[B2h] CV P
Sub-Window Y Start
Position
n/a
Bit 7
Bit 9 Bit 8
REG[B3h] PWMOUT D
RW
Bit 7
Bit 2 Bit 1 Bit 0
Notes
1 REG[00h] These bits are used to identify the S1D13706. For the S1D13706, the product code should be 10.
RW
2 REG[04h] Memory Clock Configuration Register
Sub-Window X End
Position
n/a
MCLK Divide Select Bits
Bit 9 Bit 8
RW
Bit 2 Bit 1 Bit 0
3 REG[05h] Pixel Clock Configuration Register
RW
PCLK Divide Select Bits
Sub-Window Y End
Position
n/a
Bit 9 Bit 8
RW
Power Save 4 REG[05h] Pixel Clock Configuration Register
n/a n/a Mode
Enable
PCLK Source Select Bits
RW
n/a n/a Reserved
RW 5 REG[10h] Panel Type Register
Software
n/a n/a
Reset (WO)
Panel Data Width Bits [1:0]
00
RW
01
n/a n/a n/a
10
11
RW
6 REG[10h] Panel Type Register
Bit 2 Bit 1 Bit 0 REG[10h] Bits[1:0]
RW
Bit 10 Bit 9 Bit 8
7 REG[70h] Display Mode Register
0 RW
GPIO2 Pin GPIO1 Pin GPIO0 Pin
IO Config IO Config IO Config Bit-per-pixel
Select Bits [1:0]
1 RW
000
Reserved Reserved Reserved
001
010
0 RW 011
100
GPIO2 Pin GPIO1 Pin GPIO0 Pin
IO Status IO Status IO Status
101, 110, 111
8 REG[71h] Special Effects Register
1 RW
Reserved Reserved Reserved SwivelView
RW
CV Pulse
CV Pulse CV Pulse
Burst Status
Burst Start Enable
(RO)
RW
PWMCLK
Source
Bit 1 Bit 0
Select
ULSE B URST L ENGTH R EGISTER
CV Pulse Burst Length
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
EGISTER 11
C R
UTY YCLE
PWMOUT Duty Cycle
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
BCLK to MCLK Frequency Ratio
00 1:1
01 2:1
10 3:1
11 4:1
PCLK Source to PCLK Frequency Ratio
000 1:1
001 2:1
010 3:1
011 4:1
1XX 8:1
PCLK Source
00 MCLK
01 BCLK
10 CLKI
11 CLKI2
Passive LCD Panel Data Width
Active Panel Data Width Size
Size
4-bit
8-bit
16-bit
Reserved Reserved
Panel Type
00 STN
01 TFT
10 HR-TFT
11 D-TFD
Maximum Number of Colors/Shades
Color Depth (bpp) Passive Panel
TFT Panel
(Dithering On)
1 bpp 256K/64 256K/64
2 bpp 256K/64 256K/64
4 bpp 256K/64 256K/64
8 bpp 256K/64 256K/64
16 bpp 64K/64 64K/64
Reserved n/a n/a
TM TM
Mode Select Bits SwivelView Orientation
00 Normal
01 90°
10 180°
11 270°
9 REG[B1h] PWM Clock / CV Pulse Configuration Register
RW
PWM Clock Divide Select Bits [3:0]
0h
Bit 1 Bit 0 1h
2h
3h
RW
...
Ch
Bit 1 Bit 0
Dh-Fh
10 REG[B1h] PWM Clock / CV Pulse Configuration Register
CV Pulse Divide Select Bits [2:0]
0h
1h
2h
3h
...
7h
11 REG[B3h] PWMOUT Duty Cycle Register
PWMOUT Duty Cycle [7:0]
00h
01h
02h
...
FFh
9-bit
12-bit
18-bit
Max. No. Of
Simultaneously
Displayed Colors/
Shades
2/2
4/4
16/16
256/64
64K/64
n/a
X31B-R-001-02
PWM Clock Divide Amount
1
2
4
8
...
4096
Reserved
CV Pulse Divide Amount
1
2
4
8
...
128
PWMOUT Duty Cycle
Always Low
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
...
High for 255 out of 256 clock periods
01/02/26