Epson S1D13706 Technical Manual page 273

Epson Research and Development
Vancouver Design Center
13706CFG Configuration Program
Issue Date: 01/03/29
PWMCLK
Enable
Force High
Source
Divide
Timing
Duty Cycle
Contrast Voltage Pulse
Enable
Force High
Source
Divide
Timing
Burst Length
These controls configure various PWMCLK settings.
The PWMCLK is the internal clock used by the Pulse
Width Modulator for output to the panel.
When this box is checked, the PWMCLK circuitry is
enabled.
The signal PWMOUT is forced high when this box is
checked. PWMOUT is forced low when this box is not
checked and Enable is not checked
Selects the PWMCLK source. Possible sources include
CLKI and CLKI2.
Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the PWMCLK source to
derive PWMCLK.
This field shows the actual PWMCLK frequency used
by the configuration process.
Selects the number of cycles that PWMOUT is high out
of 256 clock periods.
These controls configure various Contrast Voltage
(CV) Pulse settings. The CV Pulse is provided for
panels which support the contrast voltage function.
When this box is checked, the CV Pulse circuitry is
enabled.
The signal CVOUT is forced high when this box is
checked. CVOUT is forced low when this box is not
checked and CVOUT is not enabled.
The CV Pulse uses the same source clock as the
PWMCLK.
Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the CVOUT Pulse clock
source to derive the CV Pulse clock frequency.
This field shows the actual CV Pulse frequency used by
the configuration process.
The number of pulses generated in a single CV Pulse
burst.
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S1D13706
X31B-B-001-03