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Epson Research and Development
Vancouver Design Center
Vertical Total Register 0
REG[18h]
7
6
Vertical Total Register 1
REG[19h]
7
6
bits 9-0
Note
Vertical Display Period Register 0
REG[1Ch]
7
6
Vertical Display Period Register 1
REG[1Dh]
7
6
bits 9-0
Note
Hardware Functional Specification
Issue Date: 01/11/13
Vertical Total Bits 7-0
5
n/a
5
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
Vertical Total in number of lines = (REG[18h] bits 7:0, REG[19h] bits 1:0) + 1
1
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
2
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
Vertical Display Period Bits 7-0
5
n/a
5
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The Vertical
Display period should be less than the Vertical Total to allow for a sufficient Vertical
Non-Display period.
Vertical Display Period in number of lines = (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0) + 1
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
4
3
4
3
4
3
4
3
Read/Write
2
1
Read/Write
Vertical Total Bits 9-8
2
1
Read/Write
2
1
Read/Write
Vertical Display Period
Bits 9-8
2
1
X31B-A-001-08
Page 105
0
0
0
0
S1D13706
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