Interfacing To The Tmpr3905/12; The Toshiba Tmpr3905/12 System Bus; Overview; Card Access Cycles - Epson S1D13706 Technical Manual

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2 Interfacing to the TMPR3905/12

2.1 The Toshiba TMPR3905/12 System Bus

2.1.1 Overview

2.1.2 Card Access Cycles

S1D13706
X31B-G-002-02
The TMPR39XX family of processors features a high-speed system bus typical of modern
MIPS RISC microprocessors. This section provides an overview of the operation of the
CPU bus in order to establish interface requirements.
The TMPR3905/12 is a highly integrated controller developed for handheld products. The
microprocessor is based on the R3900 MIPS RISC processor core. The TMPR3905/12
implements an external 26-bit address bus and a 32-bit data bus allowing it to communicate
with its many peripheral units. The address bus is multiplexed (A[12:0]) using an address
latch signal (ALE) which controls the driving of the address onto the address bus. The full
26-bit address bus (A[25:0]) is generated to devices not capable of receiving a multiplexed
address, using external latches (controlled by ALE).
The TMPR3905/12 provides two, revision 2.01 compliant, PC Card slots. The 16-bit PC
Card slots provide a 26-bit multiplexed address and additional control signals which allow
access to three 64M byte address ranges: IO, memory, and attribute space. The signal
CARDREG* selects memory space when high and attribute or IO space when low.
Memory and attribute space are accessed using the write and read enable signals (WE* and
RD*). When CARDREG* is low, card IO space is accessed using separate write
(CARDIOWR*) and read (CARDIORD*) control signals.
A data transfer is initiated when the address is placed on the PC Card bus and one, or both,
of the card enable signals (CARD1CSL* and CARD1CSH*) are driven low. CARDREG*
is inactive for memory and IO cycles. If only CARD1CSL* is driven low, 8-bit data
transfers are enabled and A0 specifies whether the even or odd data byte appears on the PC
Card data bus lines D[7:0]. If only CARD1CSH* is driven low, an odd byte transfer occurs
on PC Card data lines D[15:8]. If both CARD1CSL* and CARD1CSH* are driven low, a
16-bit word transfer takes place on D[15:0].
During a read cycle, either RD* or CARDIORD* is driven low depending on whether a
memory or IO cycle is specified. A write cycle is specified by driving WE* (memory cycle)
or CARDIOWR* (IO cycle) low. The cycle can be lengthened by driving CARD1WAIT*
low for the time required to complete the cycle.
Epson Research and Development
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
Vancouver Design Center
Issue Date: 01/02/23