Figure 7-1: Clock Selection - Epson S1D13706 Technical Manual

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7.2 Clock Selection

Hardware Functional Specification

Issue Date: 01/11/13

The following diagram provides a logical representation of the S1D13706 internal clocks.

REG[05h] bits 1,0

REG[B1h] bit 0

Figure 7-1: Clock Selection

CNF[7:6] must be set at RESET#.

REG[04h] bits 5,4

REG[05h] bits 6-4

X31B-A-001-08

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