S1D13706 Hardware Configuration - Epson S1D13706 Technical Manual

Epson Research and Development
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4.2 S1D13706 Hardware Configuration

S1D13706
Pin Name
CNF[2:0]
CNF3
CNF4
CNF5
CNF[7:6]
Interfacing to the NEC VR4102 / VR4111 Microprocessors
Issue Date: 01/02/23
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to NEC VR4102/4111 interface.
Table 4-1: Summary of Power-On/Reset Configuration Options
value on this pin at the rising edge of RESET# is used to configure: (1/0)
1
100 = Generic #2 Host Bus Interface
GPIO pins as inputs at power on
Big Endian bus interface
Active high WAIT#
see Table 4-2: "CLKI to BCLK Divide Selection" for recommended setting
= configuration for NEC VR4102/VR4111
Table 4-2: CLKI to BCLK Divide Selection
CNF7 CNF6
0 0
0 1
1 0
1 1
= recommended setting for NEC VR4102/VR4111
GPIO pins as HR-TFT / D-TFT outputs
Little Endian bus interface
Active low WAIT#
CLKI to BCLK Divide
1:1
2:1
3:1
4:1
0
X31B-G-007-02
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S1D13706