Epson S1D13706 Technical Manual page 599

Epson Research and Development
Vancouver Design Center
OE, EB0-1
Interfacing to the Motorola RedCap2 DSP With Integrated MCU
Issue Date: 01/02/23
Figure 2-1: "REDCAP2 Memory Read Cycle" on page 9 illustrates a typical memory read
cycle on the REDCAP2 bus.
CLK
A[21:0]
CS
D[15:0]
R/W
Figure 2-1: REDCAP2 Memory Read Cycle
Figure 2-2: "REDCAP2 Memory Write Cycle" on page 9 illustrates a typical memory
write cycle on the REDCAP2 bus.
CLK
A[21:0]
CS
D[15:0]
R/W
OE, EB0-1
Figure 2-2: REDCAP2 Memory Write Cycle
Page 9
S1D13706
X31B-G-014-02