Table 6-24: 160X160 Sharp 'Direct' Hr-Tft Horizontal Timing - Epson S1D13706 Technical Manual

Embedded memory lcd controller
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Epson Research and Development
Vancouver Design Center
Symbol
FPLINE start position
t1
Horizontal total period
t2
FPLINE width
t3
FPSHIFT period
t4
t5
Data setup to FPSHIFT rising edge
t6
Data hold from FPSHIFT rising edge
Horizontal display start position
t7
Horizontal display period
t8
FPLINE rising edge to GPIO3 rising edge
t9
t10
GPIO3 pulse width
t11
GPIO1(GPIO0) pulse width
t12
GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge
t13
GPIO2 toggle edge to FPLINE rise edge
1. Ts
= pixel clock period
2. t1typ
= (REG[22h] bits 7-0) + 1
3. t2typ
= ((REG[12h] bits 6-0) + 1) x 8
4. t3typ
= (REG[20h] bits 6-0) + 1
5. t7typ
= ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1)
6. t8typ
= ((REG[14h] bits 6-0) + 1) x 8
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-24: 160x160 Sharp 'Direct' HR-TFT Horizontal Timing

Parameter
Min
Typ
Max
13
180
220
2
1
0.5
0.5
5
160
4
1
136
4
10
Page 77
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13706
X31B-A-001-08

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