S1D13706 Hardware Configuration; Register/Memory Mapping - Epson S1D13706 Technical Manual

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4.3 S1D13706 Hardware Configuration

S1D13706 Pin
Name
CNF[2:0]
CNF3
CNF4
CNF5
CNF[7:6]

4.4 Register/Memory Mapping

S1D13706
X31B-G-009-02
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to Motorola MPC821 microprocessor.
Table 4-2: Summary of Power-On/Reset Configuration Options
value on this pin at the rising edge of RESET# is used to configure: (1/0)
1
011 = Generic #1 Host Bus Interface
GPIO pins as inputs at power on
Big Endian bus interface
Active high WAIT#
see Table 4-3: "CLKI to BCLK Divide Selection" for recommended settings
= configuration for MPC821 microprocessor
Table 4-3: CLKI to BCLK Divide Selection
CNF7 CNF6
0 0
0 1
1 0
1 1
= recommended setting for MPC821 microprocessor
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
S1D13706 is addressed starting at 40 0000h. The S1D13706 uses two 128K byte blocks
which are selected using A14 from the MPC821 (A14 is connected to the S1D13706 M/R#
pin). The internal registers occupy the first 128K bytes block and the 80K byte display
buffer occupies the second 128K byte block.
GPIO pins as HR-TFT / D-TFT outputs
Little Endian bus interface
Active low WAIT#
CLKI to BCLK Divide
1:1
2:1
3:1
4:1
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
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Issue Date: 01/02/23