Table of Contents
Advertisement
Epson Research and Development
Vancouver Design Center
FPLINE Pulse Start Position Register 0
REG[22h]
7
6
FPLINE Pulse Start Position Register 1
REG[23h]
7
6
bits 9-0
Note
Note
FPFRAME Pulse Width Register
REG[24h]
FPFRAME
Pulse Polarity
7
6
bit 7
bits 2-0
Note
Hardware Functional Specification
Issue Date: 01/11/13
FPLINE Pulse Start Position Bits 7-0
5
n/a
5
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
n/a
5
FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be
set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel
(typically FPFRAME, SPS or DY).
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The ver-
tical sync signal is typically FPFRAME, SPS or DY, depending on the panel type.
FPFRAME Pulse Width in number of lines = (REG[24h] bits 2:0) + 1
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
4
3
4
3
4
3
Read/Write
2
1
Read/Write
FPLINE Pulse Start Position
Bits 9-8
2
1
Read/Write
FPFRAME Pulse Width Bits 2-0
2
1
X31B-A-001-08
Page 107
0
0
0
S1D13706
Advertisement
Chapters
Table of Contents
