Epson S1D13706 Technical Manual page 386

Embedded memory lcd controller

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= Required settings when used with PCI Bridge FPGA

X31B-G-004-04

The S1D13706 has 8 configuration inputs (CONF[7:0]) which are read on the rising edge

of RESET#. All S1D13706 configuration inputs are fully configurable using a ten position

DIP switch as described below.

Table 3-1: Configuration DIP Switch Settings

Value on this pin at rising edge of RESET# is used to configure:

Closed (On/1)

Select host bus interface as follows:

Note: The host bus interface is 16-bit.

Enable GPIO pins

Big Endian bus interface

WAIT# is active high

CLKI to BClk divide select:

Hardware Video Invert - invert video data

Disable FPGA for non-PCI host

To enable the Hardware Video Invert function the following are required:

• GPIO pins must be enabled (S1-4 closed).

• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).

• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1.

• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0.

• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1.

Host Bus Interface

Enable additional pins for D-TFD/HR-TFT

Little Endian bus interface

WAIT# is active low

CLKI to BClk Divide Ratio

Hardware Video Invert - normal video data

Enable FPGA for PCI host

S5U13706B00C Rev. 1.0 Evaluation Board User Manual

Epson Research and Development

Vancouver Design Center

Open (Off/0)

Issue Date: 01/02/23

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