Table 6-15: Passive/Tft Power-Off Sequence Timing; Figure 6-12: Passive/Tft Power-Off Sequence Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
6.3.2 Passive/TFT Power-Off Sequence
GPO*
Power Save
Mode Enable**
(REG[A0h] bit 0)
LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Symbol
t1
LCD bias deactivated to LCD signals inactive
t2
Power Save Mode enabled to LCD signals low
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
Hardware Functional Specification
Issue Date: 01/11/13

Figure 6-12: Passive/TFT Power-Off Sequence Timing

Table 6-15: Passive/TFT Power-Off Sequence Timing

Parameter
t1
t2
Min
Note 1
0
Page 55
Max Units
Note 1
20 ns
S1D13706
X31B-A-001-08