Figure 6-14: Generic Stn Panel Timing - Epson S1D13706 Technical Manual

Embedded memory lcd controller
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6.4.1 Generic STN Panel Timing
VPW
FPFRAME
FPLINE
1
MOD
(DRDY)
FPDAT[17:0]
FPLINE
FPSHIFT
1PCLK
2
MOD
(DRDY)
FPDAT[17:0]
S1D13706
X31B-A-001-08
VDP
HPS
HDPS
HDP

Figure 6-14: Generic STN Panel Timing

VT (= 1 Frame)
HT (= 1 Line)
Epson Research and Development
Vancouver Design Center
HPW
Hardware Functional Specification
Issue Date: 01/11/13

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