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6.4.4 Single Color 4-Bit Panel Timing
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
Notes:
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
VDP
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
VNDP
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
HDP
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
HNDP
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
S1D13706
X31B-A-001-08
LINE1
LINE2
Invalid
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
Invalid
1-R1
1-G2
1-B3
Invalid
1-G1
1-B2
1-R4
Invalid
1-B1
1-R3
1-G4
Invalid
1-R2
1-G3
1-B4
Figure 6-19: Single Color 4-Bit Panel Timing
VDP
LINE3
LINE4
LINE239 LINE240
HDP
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
2.5Ts
Epson Research and Development
Vancouver Design Center
VNDP
LINE1
LINE2
Invalid
HNDP
.5Ts
.5Ts
.5Ts
.5Ts
Invalid
1-B319
1-R320
Invalid
1-G320
Invalid
1-B320
Invalid
Hardware Functional Specification
Issue Date: 01/11/13