S1D13706 Hardware Configuration - Epson S1D13706 Technical Manual

Page 12

4.2 S1D13706 Hardware Configuration

S1D13706 Pin
Name
CNF[2:0]
CNF3
CNF4
CNF5
CNF[7:6]
S1D13706
X31B-G-016-02
The S1D13706 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13706 to Motorola MC68VZ328 microprocessor.
Table 4-1: Summary of Power-On/Reset Configuration Options
value on this pin at the rising edge of RESET# is used to configure: (1/0)
1
110 = Dragonball Host Bus Interface
GPIO pins as inputs at power on
Big Endian bus interface
Active high WAIT#
see Table 4-2: "CLKI to BCLK Divide Selection" for recommended settings
= configuration for MC68VZ328 microprocessor
Table 4-2: CLKI to BCLK Divide Selection
CNF7 CNF6
0 0
0 1
1 0
1 1
= recommended setting for MC68VZ328 microprocessor
GPIO pins as HR-TFT / D-TFT outputs
Little Endian bus interface
Active low WAIT#
CLKI to BCLK Divide
1:1
2:1
3:1
4:1
Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor
Epson Research and Development
Vancouver Design Center
0
Issue Date: 01/02/26